The present invention relates to a technique which can be effectively applied to cancellation of offsets of an input differential signal and a differential amplifier and an equalization amount of an output pre-emphasis circuit in an inter-LSI (large-scale integrated circuit) data transfer system of a network apparatus and, for example, a technique which can be effectively utilized in the network apparatus and LSIs used in the network apparatus.
Heretofore, in the inter-LSI data transfer system, the technique disclosed in JP-A-2005-20119 and JP-A-8-116340 is used to cancel a DC offset.
However, recently, a serializer/deserializer system in which bus is serialized and signal is transmitted at high speed is being often used in parts requiring the high throughput in the inter-LSI signal transmission. A main reason thereof is that in the conventional parallel transmission the operation frequency is higher the data period is shorter and it seems that timing between bits is relatively largely scattered, so that a margin of timing is small and it is hard to improve the throughput.
The serializer/deserializer system is a transceiver system for transferring data at very high speed. The serializer is a circuit for converting low-speed parallel data into high-speed serial data and transmitting the serialized data from an output buffer. The deserializer is a circuit for restoring high-speed serial data received by an input buffer to original parallel data by means of a clock data recovery circuit incorporated therein. The transceiver system using these circuits is the serializer/deserializer system. In the following description, the serializer/deserializer system is sometimes named SerDes.